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In the CDR circuit of the PON system which does bursting data playback from pulse duration distortion self method of detection and the pulse duration distortion

机译:在PON系统的CDR电路中,它从脉冲持续时间失真自身的检测方法和脉冲持续时间失真中进行突发数据回放

摘要

PROBLEM TO BE SOLVED: To provide a PON system CDR circuit incorporating the functions to self-detect and self-correct the pulse width distortion of input data by a simple method.;SOLUTION: The method includes: means 8 in which an edge phase histogram for the result of input data edge phase detection in CDR function means is created; means 11-13 in which a frequency-divided clock edge phase is detected from the result obtained by sampling, with an m-phase clock generated from a system clock, the clock which is derived from N-phase clock generation in the CDR function means by frequency-dividing it down to a system clock speed level, and a clock histogram is thereby created; and detection means 9 in which an N-phase clock jitter amount is detected from the clock histogram, and only a jitter component superposed in the input data is extracted by subtracting the clock histogram from the edge phase histogram and, from the superposed jitter component, a peak differing from an ideal 1-bit pulse width of the input data is determined to be and detected as a pulse width distortion amount.;COPYRIGHT: (C)2013,JPO&INPIT
机译:解决的问题:提供一种PON系统CDR电路,其具有通过简单方法自检测和自校正输入数据的脉宽失真的功能。解决方案:该方法包括:装置8,其中边缘相位直方图对于在CDR功能中的输入数据边缘相位检测的结果,创建了;装置11-13,其中从通过从系统时钟产生的m相时钟对CDR功能产生的时钟进行采样而获得的结果中检测出分频的时钟边缘相位通过将其分频到系统时钟速度水平,从而创建时钟直方图;检测装置9,其中从时钟直方图检测出N相时钟抖动量,并且通过从边缘相位直方图减去时钟直方图并从叠加的抖动分量中减去时钟直方图,仅提取叠加在输入数据中的抖动分量。确定一个与输入数据的理想1位脉冲宽度不同的峰值,并将其检测为脉冲宽度失真量。; COPYRIGHT:(C)2013,JPO&INPIT

著录项

  • 公开/公告号JP5575082B2

    专利类型

  • 公开/公告日2014-08-20

    原文格式PDF

  • 申请/专利权人 三菱電機株式会社;

    申请/专利号JP20110217038

  • 发明设计人 鈴木 巨生;

    申请日2011-09-30

  • 分类号H04L7/02;

  • 国家 JP

  • 入库时间 2022-08-21 16:14:44

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