Same period the latched circuit which accompanies with data load and detakiyapuchiya of asynchronism of self timing which are done

摘要

A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit.