MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND CACHE COHERENCY CONTROL PROGRAM

摘要

PROBLEM TO BE SOLVED: To reduce operations within a cache coherency mechanism.SOLUTION: A multi-core processor system 100 includes an execution unit 503 that executes coherency of the value of shared data stored in a cache memory that is accessed by each of CPUs. The multi-core processor system 100 detects a first thread executed by a CPU #0, and specifies a second thread under execution by a CPU #1 other than the CPU #0. After the specification, the multi-core processor system 100 determines whether there are shared data that are accessed by the first and second threads in common. When it is determined that there are not shared data, the multi-core processor system 100 makes the execution unit 503 stop the execution of coherency between a snooping cache #0 corresponding to the CPU #0 and a snooping cache #1 corresponding to the CPU #1.