MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND CACHE COHERENCY CONTROL PROGRAM

摘要

A multi-core processor system (100) includes an executing unit (503) that establishes coherency of shared data values stored in a cache memory accessed by each CPU. The multi-core processor system (100) detects a first thread executed by a CPU (#0) using a detecting unit (504) and identifies a second thread under execution by a CPU (#1) other than the CPU (#0). After the identification, the multi-core processor system (100) determines via a determining unit (506) whether shared data commonly accessed by the first and the second threads is present. If the multi-core processor system (100) determines that no such shared data is present, the multi-core processor system (100) causes the executing unit (503) to stop establishing coherency between a snoop supporting cache (#0) corresponding to the CPU (#0) and a snoop supporting cache (#1) corresponding to the CPU (#1).