How to use a cache memory in a system that supports a low-power state and equipment

摘要

A while low overheads of storage and complexity, to provide a cache memory system that utilizes a multi-bit error correction code (ECC). The cache memory system, while avoiding a situation in which the transition latency at the time of the start and end of the idle power state due to the fact that the state is lost is much larger, the operation of power in idle very low it is possible to. .FIELD 1