It is joined by the entry in order to accept the automatic reset (SELFRESET

摘要

SolutionsThe memory unit includes the clock buffer circuit. The aforementioned clock buffer circuit includes the cross couple logic circuit. The aforementioned cross couple logic circuit has two where the output of the inside one of the aforementioned logic gates is joined to the entry of the inside one of the aforementioned logic gates logic gates at least. The aforementioned cross couple logic circuit, in order to receive the clock pulse, is joined to entry. In addition as for the aforementioned memory unit, in order to generate the clock pulse from aforementioned output of the aforementioned cross couple logic circuit, the operational possible clock driver is included. The feedback looping to the aforementioned cross couple logic circuit controls the aforementioned cross couple logic circuit from the aforementioned clock pulse. The buffer circuit while evading the contention with the aforementioned clock generation circuit, includes 3 terminal inverter which is joined to the aforementioned clock pulse in order to maintain the aforementioned clock pulse. The aforementioned memory unit makes effective by the tip/chip selection signal. Choice figure Drawing 2