Verification support method validation support program, and verification support apparatus

摘要

PPROBLEM TO BE SOLVED: To easily specify a length of time necessary for propagating a signal between two nodes having interdependency in an object circuit without executing a simulation. PSOLUTION: When an investigation object variable (signal or register) 111, a clock signal name 112 and an RTL source code 113 for defining/referring to the variable and the name are inputted to a verification support device 100 as an input value 110, the verification support device 100 outputs a delay cycle number 121 related to the investigation object variable 111 as an output value 120. The verification support device 100 can specify the delay cycle number 121 by detecting a node on a path of the investigation object variable 111 of the RTL source code 113 for each clock domain of the respective nodes. PCOPYRIGHT: (C)2012,JPO&INPIT