Network processor with traffic shaping response bus interface

摘要

An integrated circuit is disclosed. The integrated circuit includes a receive port interface to receive request data at a first data rate from a first host and a transmit port interface. The transmit port interface to transmit response data words across plural serial lanes to a second host at a second data rate. The second data rate is less than a predefined line rate of symbol transfers across the plural serial lanes. The transmit port interface includes shaping logic to transmit a data word stream at the second data rate and selectively insert idle words into the data word stream such that the data words and the idle words are together transferred at the predefined line rate.