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Low power, high performance, heterogeneous, scalable processor architecture
Low power, high performance, heterogeneous, scalable processor architecture
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机译:低功耗,高性能,异构,可扩展的处理器体系结构
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摘要
One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
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