首页> 外国专利> Method for fabrication of an integrated circuit in a technology reduced with respect to a native technology, and corresponding integrated circuit

Method for fabrication of an integrated circuit in a technology reduced with respect to a native technology, and corresponding integrated circuit

机译:以相对于本机技术简化的技术制造集成电路的方法和相应的集成电路

摘要

The technological fabrication of the integrated circuit includes a fabrication of the integrated circuit in a reduced technological version of a native technology including at least a first dimensional compensation applied to the reduced channel length and to the reduced channel width of each transistor originating from a transistor, referred to as a “minimum transistor”, designed in the native technology and having in this native technology an initial channel length equal to a minimum length for the native technology and an initial channel width equal to a minimum width for the native technology. The fabrication obtains a transistor having a channel length equal, to a given precision, to the initial channel length and a channel width equal, to a given precision, to the initial channel width.
机译:集成电路的技术制造包括以本机技术的简化技术版本制造集成电路,该技术至少包括应用于减小的沟道长度和源自晶体管的每个晶体管的减小的沟道宽度的第一维补偿,称为“最小晶体管”,在本机技术中设计,并且在该本机技术中具有等于本机技术的最小长度的初始沟道长度和等于本机技术的最小宽度的初始沟道宽度。该制造获得具有等于给定精度等于初始沟道长度的沟道长度和等于给定精度等于初始沟道宽度的沟道宽度的晶体管。

著录项

  • 公开/公告号US8881090B2

    专利类型

  • 公开/公告日2014-11-04

    原文格式PDF

  • 申请/专利权人 GUILHEM BOUTON;VIRGINIE BIDAL;

    申请/专利号US201213618085

  • 发明设计人 GUILHEM BOUTON;VIRGINIE BIDAL;

    申请日2012-09-14

  • 分类号G06F17/50;G06F9/455;

  • 国家 US

  • 入库时间 2022-08-21 16:02:09

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