首页> 外国专利> Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter

Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter

机译:工艺流程可减少P有源区中的空穴缺陷并减少晶圆间阈值电压散布

摘要

Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.
机译:本文公开了一种形成半导体器件的方法。在一示例中,该方法包括执行至少一个蚀刻工艺以减小半导体衬底的P有源区的厚度,从而限定凹入的P有源区,在处理室中执行处理以选择性地形成As-。在凹陷的P有源区上沉积半导体材料的沉积层,其中执行至少一个蚀刻工艺的步骤在处理腔室外部执行,并在处理腔室中执行蚀刻工艺以减小as-的厚度半导体材料的沉积层。

著录项

  • 公开/公告号US8703551B2

    专利类型

  • 公开/公告日2014-04-22

    原文格式PDF

  • 申请/专利权人 STEPHAN KRONHOLZ;ANDREAS OTT;

    申请/专利号US201113102680

  • 发明设计人 ANDREAS OTT;STEPHAN KRONHOLZ;

    申请日2011-05-06

  • 分类号H01L21/00;H01L21/84;H01L21/8228;H01L21/8238;H01L21/20;H01L21/36;H01L21/302;

  • 国家 US

  • 入库时间 2022-08-21 16:01:50

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