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Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements

机译:具有最小图案密度要求的半导体技术的电感和电容元件

摘要

The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.
机译:本发明提供了一种包括多个层的半导体器件,该半导体器件包括:-具有第一主表面的衬底;-在该衬底的第一主表面上制造的感应元件,该感应元件包括至少一条导线以及,至少一个层中的多个耕作结构,其中,多个耕作结构电连接在一起并且以几何图案布置,从而基本上抑制了耕作结构中的电流对图像结构的感应。感应元件。上述半导体器件的优点在于,通过使用这种耕作结构,可以获得具有改善的品质因数的电感元件。本发明还提供一种用于在包括多个层的半导体器件中提供电感元件的方法。

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