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Digital radio frequency memory utilizing time interleaved analog to digital converters and time interleaved digital to analog converters

机译:利用时间交错的模数转换器和时间交错的数模转换器的数字射频存储器

摘要

A digital radio frequency memory (DRFM) comprises a plurality of time interleaved analog to digital converters (ADCs) in cooperation with a plurality of time interleaved digital to analog converters (DACs) to provide an effective sampling rate which may be greater than the clock rate of the system. A higher sampling rate at the ADC increases instantaneous bandwidth, while a higher sampling rate at the DAC improves spectral purity. The ADCs and DACs are time interleaved by supplying a clock signal to each ADC/DAC which is skewed with respect to the previous and subsequent skewed signal. In order to process the higher effective sampling rate, a pre-computation of DAC values for each high rate sample is performed by an SDAC algorithm that pipelines the calculations of the processed sample values provided to the DAC. A DAC bias correction is provided to adjust for drift in the DACs.
机译:数字射频存储器(DRFM)包括与多个时间交错的数模转换器(DAC)配合使用的多个时间交错的模数转换器(ADC),以提供可能大于时钟速率的有效采样率系统的。 ADC的较高采样率可增加瞬时带宽,而DAC的较高采样率可提高频谱纯度。通过向每个ADC / DAC提供相对于前一个和后一个偏斜信号偏斜的时钟信号,可以对ADC和DAC进行时间交错。为了处理更高的有效采样率,每个高采样率的DAC值都会通过SDAC算法进行预计算,该算法将提供给DAC的已处理采样值的计算流水线化。提供DAC偏置校正,以调整DAC中的漂移。

著录项

  • 公开/公告号US8659453B1

    专利类型

  • 公开/公告日2014-02-25

    原文格式PDF

  • 申请/专利权人 NATHAN E. LOW;SHAWN WALTERS;

    申请/专利号US201113082167

  • 发明设计人 SHAWN WALTERS;NATHAN E. LOW;

    申请日2011-04-07

  • 分类号H03M1/00;

  • 国家 US

  • 入库时间 2022-08-21 16:00:01

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