Generalized parallel counter structures in logic devices

摘要

Generalized parallel counter circuitry is configured from logic elements—e.g., on a programmable integrated circuit device. Each logic element includes a logic stage, an adder and an output stage. The logic stage includes logic units, and a logic stage selector for selectively outputting to an input of the adder at least one of (a) outputs of the logic units, and (b) a first logic unit output of another one of the logic elements, and for selectively outputting to the output stage one of (a) an output of the logic units, and (b) a first output of the adder. The output stage includes at least two outputs, an output selector for selectively outputting, to the at least two outputs, at least one of (a) a second output of the adder, and (b) an output of the logic stage selector.