HYBRID SINGLE AND DUAL-CHANNEL DDR INTERFACE SCHEME BY INTERLEAVING ADDRESS/CONTROL SIGNALS DURING DUAL-CHANNEL OPERATION

摘要

The memory structure is described . In one embodiment , the memory structure includes a memory controller that receives the clock signal and configured to couple to a plurality of memory modules through a single address / control bus . The memory controller is coupled to each of the plurality of memory modules through a separate chip select signal for each memory module . The memory controller issues the commands through the address / control bus to the memory modules in an interleaved manner according to the timing provided by the clock . During the waiting period after the issuing of a command to one of the memory modules , the memory controller may issue the commands to a different memory module . ;