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MINIMIZATION METHOD OF POWER TSVS AND POWER BUMPS USING FLOORPLAN BLOCK PATTERN FOR 3D POWER DELIVERY NETWORK

机译:基于Floorplan块模式的3D输电网络功率TSVS和功率波动的最小化方法

摘要

The present invention relates to a method of minimizing the number of power through electrodes and the number of power bumps using power patterns in a 3D power supply network. The method includes the steps of: inserting power through electrodes or power bumps into initially set block arrangement by taking a voltage drop into consideration and storing the number of the power through electrodes and the number of the power bumps in the initially set block arrangement; setting a grid of a die; rearranging the blocks by taking the size of the blocks and the power consumption into consideration; calculating the voltage drop on a node of the die having the re-arranged blocks and inserting the power through electrodes or the power bumps until the calculated voltage drop values of all nodes are equal to or less than a threshold value; calculating the number of the power through electrodes and the number of the power bumps when the voltage drop values of all nodes are equal to or less than the threshold value and comparing the number of the power through electrodes and the number of the power bumps in the rearranged block with the number of the power through electrodes and the number of the power bumps in the previous block; and storing the results of the rearranged blocks when the number of the power through electrodes and the number of the power bumps in the rearranged block are less than those in the previous block and storing the results of the previous block when the number of the power through electrodes and the number of the power bumps in the rearranged block are equal to or greater than those in the previous block. The steps of setting a grid having a different size and storing the result of the block arrangement are repeated until the result of the block arrangement, in which the number of through electrodes and the number of power bumps are minimized, is deduced, thereby minimizing the number of the power through electrodes and the number of power bumps inserted in order to solve the problem related to the voltage drop without the increase of the size of a die in the 3D power supply network.
机译:本发明涉及一种使用3D电源网络中的电源图案使通过电极的电源数量和电源凸块数量最小化的方法。该方法包括以下步骤:通过考虑电压降将通过电极或功率凸块的功率插入到初始设置的块布置中,并存储在初始设置的块布置中的通过电极的功率和功率凸块的数目;设置模具的网格;通过考虑块的大小和功耗来重新排列块;计算具有重新排列的块的裸片的节点上的电压降,并通过电极或功率凸块插入功率,直到计算出的所有节点的电压降值等于或小于阈值;当所有节点的电压降值均小于或等于阈值时,计算通过电极的功率数量和功率凸点的数量,并比较电极中的功率通过电极的数量和功率凸点的数量。重新排列的块,其中前一个块中的功率通过电极的数量和功率凸块的数量;当所述穿通电极的数量和所述重排块中的功率凸块的数量小于前一块中的功率凸块的数量时,存储所述重排块的结果;重新排列的块中的电极和功率凸块的数量等于或大于前一个块中的功率凸块的数量。重复设置具有不同尺寸的网格并存储块布置的结果的步骤,直到推导出其中最小化穿通电极的数量和功率凸块的数量的块布置的结果,从而最小化为了在不增加3D电源网络中裸片尺寸的情况下解决与电压降相关的问题,通过电极的电源数量和插入的电源凸点的数量。

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