Data synchronization across asynchronous boundaries using selectable synchronizers to minimize latency

摘要

A system and apparatus comprising a selectable synchronization circuit for synchronizing data across asynchronous boundaries are disclosed. The device comprises a unit that is linked to a first clock area and a synchronization sub-unit (SSU) that is coupled to the unit and is linked to a second clock area. The synchronization subunit comprises two or more synchronization units and a selection logic which is designed to select a single output of the two or more synchronization units.