Cut-to-Diagnosis (CID) - A method to improve the throughput of the yield increase process

摘要

A method of identifying a defective circuit candidate in an integrated circuit (IC) is disclosed. The method includes backtracking from at least one faulty output of the IC to determine a corresponding input cone for each faulty output using simulation values that are determined from a faultless simulation of a design of the IC. It also includes identifying a first group of suspect error candidates for each faulty outcome, each suspect error candidate potentially corresponding to a faulty element in the IC. Next, it involves forward tracking from each suspect in the first group to identify a second group of suspects, which is a smaller subset of the first group. Finally, the method comprises determining a defective block from the IC design, the defective block comprising suspect error candidates from the second group and which can be simulated independently of the complete design.