Cut-at-Diagnosis (CID) - A method to improve the throughput of the process for increasing yield

摘要

A method of generating a defective circuit candidate in an integrated circuit, the method comprising: tracing at least one defective output of the integrated circuit to determine a corresponding input cone for each defective output using simulation values derived from a faultless simulation a design of the integrated circuit; determining a first group of suspect fault candidates for each faulty output, each suspect fault candidate potentially corresponding to a defect in the integrated circuit responsible for producing a faulty result on a corresponding faulty output; tracking forward each suspect failure candidate from the first group to identify a second group of suspect failure candidates, the second group being a narrowed subset of the first group and wherein each suspect failure candidate in the second group is more likely to correspond to a defect in the integrated circuit than each suspect failure candidate in the first group; anddetermining a faulty block from the design of the integrated circuit, the faulty block comprising suspect fault candidates from the second group, and wherein the faulty block can be simulated independently of the design, the forward tracking further comprising: inputting an input stimulus to each suspect failure candidates in the first group and monitoring a response to the stimulus; comparing the response to an observed response of a chip associated with the integrated circuit with respect to the input stimulus, the observed response during a hardware test and Probing the chip is recorded; and in response to determining that the response does not match the observed response from the hardware test, excluding a suspect failure candidate from the second group.