POWER ARCHITECTURE WITH MULTIPLE VOLTAGE IDENTIFICATION (VID), DIGITALLY SYNTHETIZABLE LOW-DROPUT CONTROLLER AND DEVICE TO IMPROVE THE RELIABILITY OF POWER-GATES

摘要

An apparatus is described comprising: first and second processor cores; and a PCU operable to: generate a first VID for an off-die controller external to the device, the first VID resulting in a first power supply for the first processor core; and generating a second VID that is different from the first VID, the second VID resulting in a second power supply for the second processor core. A device is described which comprises: a plurality of power gate transistors which can be controlled by a digital bus, wherein the plurality of power gate transistors can be operated to provide a processor core with a first energy supply and a second energy supply as an input receive; an ADC to receive the first power supply and generate a digital output representative of the first power supply; and a controller to receive the digital output representing the first power supply and to generate the digital bus to control the plurality of power gate transistors.