Memory device e.g. electrically EPROM of memory system, has common wordline that is shared by gate terminals of transistors included in memory cells in row share, which is adapted to provide signal to gate terminals

摘要

The device (200A) has source lines (VSP1-VSP4) that are associated with memory sections (210,220,230) having memory cells (212,214,222,232,234) arranged in rows and columns. The source terminals of transistors (212a,212b) included in memory cells in first storage section, are coupled to first source line, which is different from other source lines. The other memory sections in same row of device are associated as the first storage section. A common wordline (WL1-WL4) is shared by gate terminals of transistors included in cells in a row share, which provides signal to gate terminals. An independent claim is included for a memory system.