LAYOUT VERIFICATION METHOD, VERIFICATION LAYOUT DATA CREATION METHOD, LAYOUT VERIFICATION PROGRAM, AND VERIFICATION LAYOUT DATA GENERATION PROGRAM

摘要

PROBLEM TO BE SOLVED: To provide a layout verification method, verification layout data creation method, layout verification program, and verification layout data creation program, which allow efficient verification of the layout of a three-dimensional LSI chip.SOLUTION: A layout verification method for verifying the layout of a three-dimensional semiconductor includes: a virtual layer synthesis step in which the layout data of an uppermost layer in the layout data of a plurality of layers that has location information of a plurality of elements including a via and wiring pattern in a first semiconductor device and has identical node information for the plurality of elements having an identical potential is added for synthesis as the layout data of a virtual layer to the layout data of a second semiconductor device that is laminated on the first semiconductor device; and an error detection step in which an error is detected when there is different node information for the plurality of elements with an identical potential in the layout data of the second semiconductor device which includes the virtual layer.