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BUS CONTROL CIRCUIT, INFORMATION PROCESSOR, AND COMMON BUS COLLISION AVOIDANCE METHOD

机译:总线控制电路,信息处理器和常见总线冲突回避方法

摘要

PROBLEM TO BE SOLVED: To prevent an abnormality of one of a plurality of control circuits from causing a situation in which a normal control circuit cannot use a common bus.SOLUTION: The bus control circuit 1 includes an abnormality detection circuit 2 and an adjusting circuit 3. The abnormality detection circuit 2 detects the abnormality of bus control signals S1 and S2 for reporting whether control circuits 5 and 6 demand the use of a common bus 7. The adjusting circuit 3 includes a logic circuit for creating a signal for controlling the flow of data D1 and D2 from respective control circuits 5 and 6 to the common bus 7 on the basis of the bus control signals S1 and S2 output from respective control circuits 5 and 6, presence/absence of abnormality detection by the abnormality detection circuit 2, and a previously determined priority of use of the common bus 7.
机译:解决的问题:为了防止多个控制电路之一的异常引起正常控制电路不能使用公共总线的情况。解决方案:总线控制电路1包括异常检测电路2和调节电路。 3.异常检测电路2检测总线控制信号S1和S2的异常,以报告控制电路5和6是否要求使用公共总线7。调节电路3包括用于产生用于控制流量的信号的逻辑电路。基于从各个控制电路5和6输出的总线控制信号S1和S2,从各个控制电路5和6到公共总线7的数据D1和D2的变化,由异常检测电路2进行的异常检测的有无。以及先前确定的公共总线使用优先级7。

著录项

  • 公开/公告号JP2015135599A

    专利类型

  • 公开/公告日2015-07-27

    原文格式PDF

  • 申请/专利权人 NEC ENGINEERING LTD;

    申请/专利号JP20140006774

  • 发明设计人 MANO NORIHITO;

    申请日2014-01-17

  • 分类号G06F13/36;G06F13/362;G06F13/42;

  • 国家 JP

  • 入库时间 2022-08-21 15:34:24

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