SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD, FAILURE DETECTION PROBABILITY IMPROVEMENT METHOD, TEST POINT CONFIGURATION METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD

摘要

PROBLEM TO BE SOLVED: To provide a failure detection probability improvement method, point configuration method, and semiconductor integrated circuit design method which facilitate creating test patterns having a high transition failure detection rate.;SOLUTION: An arithmetic processing unit 10 of a semiconductor integrated circuit includes: a controllability probability calculation unit 11 that calculates a controllability probability to a failure for two consecutive system clock cycles for an input/output port of each gate on a logic circuit in the semiconductor integrated circuit; an observability probability calculation unit 12 that refers to the controllability probability and calculates the observability probability of the input/output port for the two consecutive system clock cycles; a test point selection unit 13 that performs a first step or first and second steps and determines a test point on the basis of a value of the controllability probability and/or observability probability; and an insertion circuit inserting unit 14 that inserts an insertion circuit for improving a failure detection rate into the selected test point.;COPYRIGHT: (C)2015,JPO&INPIT