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Test condition setting method, current fluctuation test method, and information processing apparatus

机译:试验条件设定方法,电流变动试验方法及信息处理装置

摘要

A master CPU makes an execution interval b, during which CPUs are operated, common to CPUs including the master CPU and makes a stop interval a, during which the CPUs are stopped, different for each of the CPUs including the master CPU. As a result, the lengths of cycle intervals c of the CPUs constituted by the execution interval b and the stop interval a allow the ratio between the lengths of the cycle intervals c of any CPUs to be represented by two integers that are coprime to each other. Setting such lengths of the cycle intervals c of the CPUs achieves the synchronism between the shifts of all of the CPUs from a stopped state to an in-operation state and from the in-operation state to the stopped state.
机译:对于包括主CPU的每个CPU,主CPU使执行间隔b和执行停止间隔a不同,执行间隔b对CPU进行操作,该执行间隔b在该操作间隔b期间对于包括该主CPU的CPU而言是公用的。结果,由执行间隔b和停止间隔a构成的CPU的周期间隔c的长度允许任何CPU的周期间隔c的长度之间的比率由彼此互质的两个整数表示。 。设置CPU的周期间隔c的这种长度实现了所有CPU从停止状态到操作状态以及从操作状态到停止状态的转换之间的同步。

著录项

  • 公开/公告号JP5724772B2

    专利类型

  • 公开/公告日2015-05-27

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20110195309

  • 发明设计人 寺西 信輔;

    申请日2011-09-07

  • 分类号G06F9/48;G06F1/28;G06F1/30;G06F1/26;

  • 国家 JP

  • 入库时间 2022-08-21 15:30:05

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