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Josephson junction array structure, digital-to-analog converter and superconducting voltage standard circuit using the structure

机译:约瑟夫逊结阵列结构,数模转换器和使用该结构的超导电压标准电路

摘要

PROBLEM TO BE SOLVED: To solve the problem in a Josephson junction array structure that since operation margin considerably decreases when the number of junctions is increased, the output voltage of a superconducting digital to analog converter is low by preventing reduction in an operation margin due to high degree of integration and heat generation in a Josephson junction array structure with as high impedance as 100 Ω.;SOLUTION: A Josephson junction array structure of the present invention comprises a Josephson junction array and an external conductor disposed on both sides thereof. The Josephson junction array is such that two adjacent Josephson junctions are connected sharing one bottom electrode, and that the bottom electrode includes a wide part extending from the Josephson junction to the external conductor and a narrow part at a position where the adjacent Josephson junctions are connected. The bottom electrode having the narrow part and sufficiently large in size helps to achieve a high line impedance, making it possible to restrict the attenuation of an electromagnetic pulse signal due to junction resistance.;COPYRIGHT: (C)2013,JPO&INPIT
机译:要解决的问题:为了解决约瑟夫森结阵列结构中的问题,因为当结数增加时,操作裕度会显着降低,因此,超导数模转换器的输出电压会因防止由于具有高达100Ω的高阻抗的约瑟夫森结阵列结构具有高集成度和发热。解决方案:本发明的约瑟夫森结阵列结构包括约瑟夫森结阵列和设置在其两侧的外部导体。约瑟夫森结阵列使得两个相邻的约瑟夫森结连接在一起并共享一个底部电极,并且该底部电极包括从约瑟夫森结延伸到外部导体的宽部分和在相邻的约瑟夫森结连接的位置处的狭窄部分。底部电极具有狭窄的部分并且尺寸足够大,有助于实现高线阻抗,从而可以限制由于结电阻而引起的电磁脉冲信号的衰减。;版权所有:(C)2013,JPO&INPIT

著录项

  • 公开/公告号JP5709168B2

    专利类型

  • 公开/公告日2015-04-30

    原文格式PDF

  • 申请/专利权人 独立行政法人産業技術総合研究所;

    申请/专利号JP20110168231

  • 发明设计人 山森 弘毅;

    申请日2011-08-01

  • 分类号H01L39/22;

  • 国家 JP

  • 入库时间 2022-08-21 15:29:01

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