The III-V engineered substrate manufacturing method and a group III-V engineered substrate of

摘要

Manufacturing an III-V engineered substrate involves providing a base substrate (I) comprising an upper layer (2) made of a first III-V compound with a 110 or a 111 crystal orientation, forming an intermediate layer (II) comprising forming at least a buffer layer (3) of a second III-V compound, wherein the intermediate layer (II) is overlying and in contact with the upper layer (2) of the base substrate. Then a pseudomorphic passivation layer (4) made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer (II). This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.