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PRECISION HALF CELL FOR SUB-FEMTO UNIT CAP AND CAPACITIVE DAC ARCHITECTURE IN SAR ADC

机译:SAR ADC中次微型单位电容和电容DAC架构的精密半单元

摘要

A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.
机译:公开了一种电容装置,包括形成在下部金属层上并耦合到第一端子的第一导体。第二导体形成在上部金属层上,并且多条导线被分成几组,每组包括来自相应金属层的一根导线。每组的第一和第二导线耦合到第二端子。与第一导线相邻的每组的第三导线耦合到第一导体。与第二导线相邻的每组的第四导线耦合到第二导体。所述组的第一子集的第五导线耦合到第二导体,并且所述组的第二子集的第五导线耦合到第一导体。每组的第五根线与第一根线和第二根线相邻。

著录项

  • 公开/公告号US2015263754A1

    专利类型

  • 公开/公告日2015-09-17

    原文格式PDF

  • 申请/专利权人 APPLE INC.;

    申请/专利号US201514643478

  • 申请日2015-03-10

  • 分类号H03M1/46;H01G4/01;H01G4/12;H01G4/228;

  • 国家 US

  • 入库时间 2022-08-21 15:26:48

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