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HYSTERESIS COMPARATOR CIRCUIT HAVING DIFFERENTIAL INPUT TRANSISTORS WITH SWITCHED BULK BIAS VOLTAGES

机译:滞回比较器电路,具有带开关的批量偏置电压的差分输入晶体管

摘要

A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.
机译:考虑到磁滞值,将在第一晶体管处接收到的第一信号与在第二晶体管处接收到的第二信号进行比较,以产生比较输出。第一和第二晶体管中的至少一个具有浮体。开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮体。设置磁滞值的第三和第四输入信号在第三和第四晶体管处接收,并进行比较以产生差分输出。第三和第四晶体管中的至少一个具有浮体。差分放大器确定差分输出之间的差,以施加到第三和第四晶体管中的至少一个的浮置体,并进一步用作第一和第二体偏置电压中的一个。

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