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METHOD AND APPARATUS FOR REDUCED PARASITICS AND IMPROVED MULTI-FINGER TRANSISTOR THERMAL IMPEDANCE
METHOD AND APPARATUS FOR REDUCED PARASITICS AND IMPROVED MULTI-FINGER TRANSISTOR THERMAL IMPEDANCE
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机译:减小寄生和改进的多指晶体管热阻抗的方法和装置
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摘要
A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, providing for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance.
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