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MULTI-CORE COMPUTER PROCESSOR BASED ON A DYNAMIC CORE-LEVEL POWER MANAGEMENT FOR ENHANCED OVERALL POWER EFFICIENCY
MULTI-CORE COMPUTER PROCESSOR BASED ON A DYNAMIC CORE-LEVEL POWER MANAGEMENT FOR ENHANCED OVERALL POWER EFFICIENCY
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机译:基于动态核级功率管理的多核计算机处理器,可提高整体功率效率
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摘要
The present disclosure provides methods and systems for managing power in a processor having multiple cores. In one implementation, a microarchitecture of a core within a general-purpose processor may include configurable lanes (horizontal slices through the pipeline) which can be powered on and off independently from each other within the core. An online optimization algorithm may determine within a reasonably small fraction of a time slice a combination of lanes within different cores of the processor to be powered on that optimizes performance under a power constraint budget for the workload running on the general-purpose processor. The online optimization algorithm may use an objective function based on response surface models constructed to fit to a set of sampled data obtained by running the workload on the general-purpose processor with multiple cores, without running the full workload. In other implementations, the power supply to lanes can be gated.
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