SELECTIVE CONTROL OF ON-CHIP DEBUG CIRCUITRY OF EMBEDDED PROCESSORS

摘要

An apparatus includes a first circuit portion, a second circuit portion, and a control circuit. The first circuit portion may include a first debug circuit. Access to the first debug circuit may be controlled by a first control signal. The second circuit portion may include a second debug circuit. Access to the second debug circuit may be controlled by a second control signal. The second circuit portion is generally controlled according to a secure firmware image. The control circuit may be configured to selectively disable access to the first debug circuit and access to the second debug circuit by generating the first and second control signals. When access to the second debug circuit is disabled, access to the second debug circuit can only be re-enabled by overwriting at least a portion of the secure firmware image.