首页>
外国专利>
System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator
System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator
展开▼
机译:通过使用相位插值器的精细训练来改善高速I / O互连链路的系统时序余量
展开▼
页面导航
摘要
著录项
相似文献
摘要
Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.
展开▼