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Method of in-process intralayer yield detection, interlayer shunt detection and correction
Method of in-process intralayer yield detection, interlayer shunt detection and correction
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机译:工艺内层间良率检测,层间并联检测及校正的方法
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摘要
A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
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