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Increased error correction for cache memories through adaptive replacement policies

机译:通过自适应替换策略提高对缓存的错误纠正

摘要

A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.
机译:一种通过减少高速缓存中脏线的驻留时间来降低高速缓存的整体可检测的不可恢复FIT率的系统,处理器和方法。这是通过在执行期间根据系统的DUE FIT目标有选择地选择不同的替换策略来实现的。在有效降低DUE FIT率的同时,对系统性能和功耗的影响降至最低。

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