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ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER
ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER
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机译:鲁棒的数值优化,优化延迟,面积和泄漏功率
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摘要
Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.
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