METHOD OF MANUFACTURING AN ELECTRONIC STRUCTURE COMPRISING REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION AND CORRESPONDING ELECTRONIC STRUCTURE

摘要

A technique is disclosed for causing the top surfaces of solder bumps on a chip (40) to be in the same plane to ensure a more reliable bond between the chip (40) and a substrate (62). The chip (40) is provided with solder pads (42, 44) that may have different heights. A dielectric layer (50) is formed between the solder pads (42, 44). A relatively thick metal layer (52) is plated over the solder pads (42, 44). The metal layer (52) is planarized to cause the top surfaces of the metal layer (52) portions over the solder pads (42, 44) to be in the same plane and above the dielectric layer (50). A substantially uniform thin layer of solder (58) is deposited over the planarized metal layer portions (52) so that the top surfaces of the solder bumps are substantially in the same plane, which may be substantially parallel to the top surface of the chip (40) or at an angle relative to the top surface of the chip (40). The chip (40) is then positioned over a substrate (62) having corresponding metal pads (64), and the solder (58) is reflowed or ultrasonically bonded to the substrate pads (64).