METHOD OF MANUFACTURING AN ELECTRONIC STRUCTURE COMPRISING REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION AND CORRESPONDING ELECTRONIC STRUCTURE

摘要

A technique is disclosed for ensuring that the top surfaces of the solder bumps on the chip 40 are coplanar to ensure a more reliable bond between the chip 40 and the substrate 62. The chip 40 has solder pads 42 and 44 that can have different heights. A dielectric layer 50 is formed between the solder pads 42 and 44. A relatively thick metal layer 52 is plated over the solder pads 42 and 44. The metal layer 52 is planarized so that the top surface of the portion of the metal layer 52 over the solder pads 42 and 44 is coplanar and over the dielectric layer 50. A substantially uniform thin layer of solder 58 is substantially uniform in which the upper faces of the solder bumps can be substantially parallel to the upper face of the chip 40 or angled relative to the upper face of the chip 40. To be coplanar, it is deposited over the planarized metal layer portion 52. The chip 40 is then placed over the substrate 62 with the corresponding metal pads 64 and the solder 58 is reflowed or ultrasonically bonded to the substrate pads 64.