首页> 外国专利> Methods and apparatus for building bus interconnection networks using programmable interconnection resources

Methods and apparatus for building bus interconnection networks using programmable interconnection resources

机译:使用可编程互连资源建立总线互连网络的方法和装置

摘要

Integrated circuits may include logic regions configurable to perform custom functions. Interconnects (16, 16C, 16D, 16E) may be used to route signals throughout the integrated circuit. The logic region (34) may be coupled to input selection circuitry (55) for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry (56) for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry (38) may provide direct access to registers inside the logic regions (34) and to the output selection and routing circuitry (56) by bypassing the input selection circuitry and other processing circuitry inside the logic regions (34). Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.
机译:集成电路可以包括可配置为执行定制功能的逻辑区域。互连(16、16C,16D,16E)可用于在整个集成电路中路由信号。逻辑区域(34)可以耦合到输入选择电路(55),用于选择并提供从互连到逻辑区域的输入信号;以及输出选择和路由电路(56),用于选择并通过互连将输出信号传输到其他逻辑。地区。旁路电路(38)可以通过绕过逻辑区域(34)内的输入选择电路和其他处理电路来提供对逻辑区域(34)内的寄存器以及对输出选择和路由电路(56)的直接访问。可以通过适当地配置旁路电路以及输出选择和路由电路来生成具有执行寄存器流水线,引线缝合以及充当数据源/接收站以接通和断开总线互连的逻辑区域的总线互连。

著录项

  • 公开/公告号EP2722989A3

    专利类型

  • 公开/公告日2015-07-01

    原文格式PDF

  • 申请/专利权人 ALTERA CORPORATION;

    申请/专利号EP20130188528

  • 发明设计人 HUTTON MICHAEL D.;

    申请日2013-10-14

  • 分类号H03K19/177;

  • 国家 EP

  • 入库时间 2022-08-21 15:06:03

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号