LDPC decoding using different quantization for check node and variable node processing

摘要

A low density parity check decoder is provided that includes a variable-node (VN) processing domain comprising high-bit resolution (high-precision quantisation) processing circuitry, a check-node (CN) processing domain comprising low-bit resolution (low-precision quantisation) processing circuitry lower than the high-bit resolution processing circuitry, and mapping circuitry configured to transfer a message between the VN processing quantisation domain and the CN processing quantisation domain.