Method, system and computer program product for characterizing the variability of an integrated circuit design

摘要

The present disclosure provides method, system and computer program product for characterizing variability of an integrated circuit design in a target semiconductor manufacturing process. A timing report of the integrated circuit design is provided from an existing description of the integrated circuit design. The existing description results from synthesis of the integrated circuit design in the target semiconductor manufacturing process. A set of relevant standard cells is determined in one or more data paths of the existing integrated circuit design on the basis of the timing report. The relevant standard cells are statistically characterised, thereby generating for each relevant standard cell a first statistically relevant number N of variants of its cell netlist. The timing report of the integrated circuit design is recalculated at least a second statistically relevant number M times, wherein these variants are reused.