DISTRIBUTED DISPATCH WITH CONCURRENT, OUT-OF-ORDER DISPATCH

摘要

In one embodiment of the present invention, the processor 10 includes an instruction buffer 20 and a pick unit 26. [ The instruction buffer is connected to receive instructions fetched from the instruction cache. The pick unit selects a maximum of N instructions from the instruction buffer 20 for simultaneous transmission to each slot of a plurality of slots 34A-34D, where N is an integer greater than one. Also, the pick unit 26 transmits the oldest instruction among the selected instructions to any one of the plurality of slots 34A-34D even if the number of the selected instructions is greater than one. The pick unit 20 simultaneously transmits other ones of the selected instructions to the other of the plurality of slots 34A-34D based on the slot to which the oldest instruction is transmitted.;Pick unit, dispatch, instruction, processor