However plurality of shift registers (SR1, SR2, ..., SRn) is the i-th circuit with cascaded ( 1a, 1b) (i is 1iN (N is an integer of 2 or more) and , respectively) of an integer , each of the i-th circuit (1a, 1b) are dedicated to each of the i-th circuit (1a, 1b) supply line (10b, 10c, 10e, 10f) each of the shift register stage by (SR1, SR2, ..., SRn) drive signals for driving the (CKA1, CKA2, CKB1, CKB2) the first circuit is supplied (1a , 1b) and the supply line (10b, 10c, 10e, 10f) is provided with a .
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