APPARATUS AND METHOD FOR EXTRACTING VERTICAL GRAIN BOUNDARY LOCATION OF LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR USING CAPACITANCE-VOLTAGE CHARACTERISTICS

摘要

The present invention is to provide an apparatus and a method for extracting a grain boundary location finally by obtaining a width of a valid depletion area through a depletion capacitance varying depending on the location of the grain boundary using a difference between a capacitance-voltage characteristics of a case in which the grain boundary does not exist in a polycrystalline thin film transistor and a capacitance-voltage characteristics of a case in which the grain boundary exists. The apparatus of the present invention includes: a C-V characteristics detection part which detects the capacitance-voltage characteristics of a device where the grain boundary exists in a channel; a capacitance value extraction part which extracts a capacitance value in case a gate voltage corresponding to an amplitude capable of forming a depletion area on the basis of the detected capacitance-voltage characteristics is applied; a depletion capacitance extracting part which separates and extracts the depletion capacitance varying depending on the location of the grain boundary from the extracted capacitance value; and a grain boundary location calculation part which calculates a vertical location of the grain boundary from the thickness of the depletion area by calculating the width of the valid depletion area from the separated and extracted depletion capacitance.;COPYRIGHT KIPO 2016