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voltage controlled oscillator PLL circuit clock generator and HDMI TX PHY

机译:压控振荡器PLL电路时钟发生器和HDMI TX PHY

摘要

phase locked loop circuit includes a phase frequency detector, a first signal path, a second signal path, and a voltage controlled oscillator It includes. Phase / frequency detector is based on the phase difference and frequency difference between the reference signal and the output signal generates an up / down signal. The first signal path provides a first oscillator control signal proportional to the up / down signal. The second signal path provides a second oscillation control signal represented by the integral function of the up / down signal. Voltage controlled oscillator generates an output signal whose frequency is changed in response to the regulated voltage signal appearing at a constant combination of the first oscillation control signal and the second oscillation control signal by receiving the first oscillation control signal and the second oscillation control signal independently thereby.
机译:锁相环电路包括相位频率检测器,第一信号路径,第二信号路径和压控振荡器。鉴相器/鉴频器是根据参考信号和输出信号之间的相位差和频率差产生一个上/下信号。第一信号路径提供与上/下信号成比例的第一振荡器控制信号。第二信号路径提供由上/下信号的积分函数表示的第二振荡控制信号。压控振荡器通过独立地接收第一振荡控制信号和第二振荡控制信号来生成输出信号,该输出信号的频率响应于稳定电压信号出现在第一振荡控制信号和第二振荡控制信号的恒定组合处而改变频率。 。

著录项

  • 公开/公告号KR101566417B1

    专利类型

  • 公开/公告日2015-11-05

    原文格式PDF

  • 申请/专利权人 삼성전자주식회사;

    申请/专利号KR20080085031

  • 发明设计人 박재현;신종신;

    申请日2008-08-29

  • 分类号H03L7/099;

  • 国家 KR

  • 入库时间 2022-08-21 14:57:27

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