Integral fabrication of asymmetric CMOS transistors for autonomous wireless state radio systems and sensor / actuator nodes

摘要

A method of arranging asymmetrically doped CMOS transistors in a semiconductor wafer, wherein basic cells are formed in a plurality of logic standard cells in a CMOS process technology, comprising conventional balanced CMOS transistors having different threshold voltages. The asymmetrically doped CMOS transistors have a gate length of more than 1.5 times the minimum gate length of the balanced CMOS transistors. The regions defined by the electrical junctions immediately adjacent the gate of the asymmetric transistors are formed by an implant mask exposing a portion of the wafer on the source side of the transistor to accommodate the transient implantation of the higher threshold voltage balanced CMOS transistors while shielding the drain region and another implant mask exposing a portion of the wafer on the drain side of the transistor to accommodate the transient implantation of the lower threshold voltage balanced CMOS transistors while shielding the source region.