首页> 外国专利> METHOD FOR MANUFACTURING AN AREA PIN CORRUGATED AND SPACED DOPED ZONES, APPLICATION TO THE MANUFACTURE OF ELECTRO-OPTICAL SILICON MODULATORS AND GERMANIUM PHOTO-DETECTORS

METHOD FOR MANUFACTURING AN AREA PIN CORRUGATED AND SPACED DOPED ZONES, APPLICATION TO THE MANUFACTURE OF ELECTRO-OPTICAL SILICON MODULATORS AND GERMANIUM PHOTO-DETECTORS

机译:制造带销的波纹状和带间隔的掺杂区的方法,在光电硅调制器和锗光电探测器的制造中的应用

摘要

The invention relates to a method of manufacturing a PIN edge junction (20, 21) of semiconductor material. According to the invention, a judicious choice is made for definition of hard masks and concatenation of formation of resin masks for implantation (doping) and etching, which makes it possible to use the usual photo-lithography technique despite its weak Alignment accuracy (+/- 100nm) of the masks compared to the areas below. With the method according to the invention, the formation of an edge pin junction is obtained, at lower cost and in a shorter time than the state of the art, with doped zones precisely spaced from the edge of the ridge.
机译:本发明涉及一种制造半导体材料的PIN边缘结(20、21)的方法。根据本发明,对于硬掩模的定义以及用于注入(掺杂)和蚀刻的树脂掩模的形成的级联做出了明智的选择,尽管对准精度较差(+ /,但仍可以使用常规的光刻技术)。 -100nm)的掩模与下面的区域相比。利用根据本发明的方法,与现有技术相比,以较低的成本和更短的时间获得了边缘销结的形成,其中掺杂区与脊的边缘精确地间隔开。

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