CONFIGURABLE PAPILLON DIGITAL DATA PROCESSING PROCESSOR BETWEEN FFT / IFFT CALCULATION AND CHANNEL DECODING AND CORRESPONDING TELECOMMUNICATION DEVICE

摘要

The digital data processing processor (80) has at least one butterfly operator (82) configurable between a first configuration in which the throttle operator performs a fast Fourier transform calculation and a second configuration in which the throttle operator performs a calculating metrics of an implementation of a channel decoding algorithm. This throttle operator has an architecture comprising material add / subtract modules (40 ', 42', 48 ', 50'), each including several elementary addition / subtraction modules. These hardware add / subtract modules (40 ', 42', 48 ', 50') are configurable using at least one programmable parameter (cmd) for selecting an addition / subtraction dynamics among several dynamics of addition / subtraction possible between a maximal dynamic according to which a single computation of maximum size addition / subtraction of the operands is realized by the set of cascaded elementary modules and a minimal dynamics according to which several independent computations of addition Minimal size subtraction of the operands is performed by each of the elementary modules in parallel.