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HIGH UTILIZATION UNIVERSAL LOGIC ARRAY WITH VARIABLE CIRCUIT TOPOLOGY AND LOGISTIC MAP CIRCUIT TO REALIZE A VARIETY OF LOGIC GATES WITH CONSTANT POWER SIGNATURES
HIGH UTILIZATION UNIVERSAL LOGIC ARRAY WITH VARIABLE CIRCUIT TOPOLOGY AND LOGISTIC MAP CIRCUIT TO REALIZE A VARIETY OF LOGIC GATES WITH CONSTANT POWER SIGNATURES
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机译:具有可变电路拓扑和逻辑地图电路的高利用率通用逻辑阵列,可实现具有恒定功率签名的各种逻辑门
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摘要
Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.
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