首页> 外国专利> HIGH UTILIZATION UNIVERSAL LOGIC ARRAY WITH VARIABLE CIRCUIT TOPOLOGY AND LOGISTIC MAP CIRCUIT TO REALIZE A VARIETY OF LOGIC GATES WITH CONSTANT POWER SIGNATURES

HIGH UTILIZATION UNIVERSAL LOGIC ARRAY WITH VARIABLE CIRCUIT TOPOLOGY AND LOGISTIC MAP CIRCUIT TO REALIZE A VARIETY OF LOGIC GATES WITH CONSTANT POWER SIGNATURES

机译:具有可变电路拓扑和逻辑地图电路的高利用率通用逻辑阵列,可实现具有恒定功率签名的各种逻辑门

摘要

A new circuit is disclosed that is capable of generating any logic combination possible as a function of the input logic signal. The circuit is described as a two-input logistic map circuit, but can be extended to more than three inputs as needed. A general purpose logic array with a variable circuit topology is also disclosed. A circuit topology that implements a metal layer and / or via interconnected Boolean function and / or a chaotic function and / or a logic function between cells in the array element. The new circuit provides a circuit topology for security applications with input and output mappings, with no apparent physical correspondence between control signal values. Also disclosed is a network having independent power signatures for input signal status and output switching. This provides a very useful circuit for protecting data from decryption from power signatures analysis in security applications.;
机译:公开了一种新电路,其能够根据输入逻辑信号生成任何可能的逻辑组合。该电路被描述为两输入逻辑映射电路,但是可以根据需要扩展到多于三个输入。还公开了具有可变电路拓扑的通用逻辑阵列。一种电路拓扑,可实现金属层和/或通过互连的布尔函数和/或混沌函数和/或阵列元素中单元之间的逻辑函数实现。新电路为具有输入和输出映射的安全应用提供了电路拓扑,控制信号值之间没有明显的物理对应关系。还公开了具有用于输入信号状态和输出切换的独立功率签名的网络。这提供了一个非常有用的电路,用于保护数据免受安全应用中电源签名分析的解密。

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